Architectures for an Implantable Medical Device System

ABSTRACT

An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. patent application Ser. No. 11/767,636,filed Jun. 25, 2007, to which priority is claimed and which isincorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates generally to implantable medical devices,and more particularly, to improved architectures for the circuitry in animplantable medical device.

BACKGROUND

Implantable stimulation devices are devices that generate and deliverelectrical stimuli to body nerves and tissues for the therapy of variousbiological disorders, such as pacemakers to treat cardiac arrhythmia,defibrillators to treat cardiac fibrillation, cochlear stimulators totreat deafness, retinal stimulators to treat blindness, musclestimulators to produce coordinated limb movement, spinal cordstimulators to treat chronic pain, cortical and deep brain stimulatorsto treat motor and psychological disorders, and other neural stimulatorsto treat urinary incontinence, sleep apnea, shoulder sublaxation, etc.The present invention may find applicability in all such applications,although the description that follows will generally focus on the use ofthe invention within a Spinal Cord Stimulation (SCS) system, such asthat disclosed in U.S. Pat. No. 6,516,227 (“the '227 patent”), which isincorporated herein by reference in its entirety.

Spinal cord stimulation is a well-accepted clinical method for reducingpain in certain populations of patients. As shown in FIGS. 1A and 1B, aSCS system typically includes an Implantable Pulse Generator (IPG) 100,which includes a biocompatible case 30 formed of titanium for example.The case 30 usually holds the circuitry and power source or batterynecessary for the IPG to function. The IPG 100 is coupled to electrodes106 via one or more electrode leads (two such leads 102 and 104 areshown), such that the electrodes 106 form an electrode array 110. Theelectrodes 106 are carried on a flexible body 108, which also houses theindividual signal wires 112, 114, coupled to each electrode. The signalwires 112 and 114 are connected to the IPG 100 by way of an interface115, which may be any suitable device that allows the leads 102 and 104(or a lead extension, not shown) to be removably connected to the IPG100. Interface 115 may comprise, for example, an electro-mechanicalconnector arrangement including lead connectors 38 a and 38 b configuredto mate with corresponding connectors 119 a and 119 b on the leads 102and 104. In the illustrated embodiment, there are eight electrodes onlead 102, labeled E₁-E₈, and eight electrodes on lead 104, labeledE₉-E₁₆, although the number of leads and electrodes is applicationspecific and therefore can vary. The electrode array 110 is typicallyimplanted along the dura of the spinal cord, and the IPG 100 generateselectrical pulses that are delivered through the electrodes 106 to thenerve fibers within the spinal column. The IPG 100 itself is thentypically implanted somewhat distantly in the buttocks of the patient.

As shown in FIG. 2, an IPG 100 typically includes an electronicsubstrate assembly 14 including a printed circuit board (PCB) 16, alongwith various electronic components 20, such as microprocessors,integrated circuits, and capacitors, mounted to the PCB 16. Ultimately,the electronic circuitry performs a therapeutic function, such asneurostimulation. A feedthrough assembly 24 routes the various electrodesignals from the electronic substrate assembly 14 to the lead connectors38 a, 38 b, which are in turn coupled to the leads 102 and 104 (seeFIGS. 1A and 1B). The IPG 100 further comprises a header connector 36,which among other things houses the lead connectors 38 a, 38 b. The IPG100 can further include a telemetry antenna or coil 96 (FIG. 1A) mountedwithin the header connector 36 for transmission and receipt of data toand from an external device such as a hand-held or clinician programmer(not shown). As noted earlier, the IPG 100 usually also includes a powersource 26, usually a rechargeable battery 26. The power source 26 can berecharged transcutaneously by an external charger 12. Specifically, whenactive during a charging session, the external charger 12 energizes itscharging coil 17, which in turn induces a current in the charging coil18 in the IPG 100. This induced current is rectified and ultimately usedto charge the power source 26 through the patient's flesh 25.

Further details concerning the structure and function of typical IPGsand IPG systems are disclosed in U.S. patent application Ser. No.11/305,898, filed Dec. 14, 2005, which is incorporated herein byreference.

A traditional architecture 50 for the circuitry inside of an IPG 100 isshown in FIG. 3. As one skilled in the art will appreciate, FIG. 3depicts the IPG 100's circuitry at a relatively high level sufficient tounderstand the points this disclosure makes. The architecture 50contains basic circuit blocks for executing various electrical functionsin the IPG 100. For example, telemetry circuit 62 is coupled to coil 96,and operates to send and receive data to and from an external controller(not shown). Charging and battery protection circuitry 64 is similarlycoupled to charging coil 18, and intervenes between the power source 26and the rest of the circuitry. Both of these circuits 62 and 64 arecoupled to a microcontroller 60, which as can be noticed is central tothe design of the architecture 50. Programs and data needed by themicrocontroller 60 upon power up are stored in a memory 66, preferably aserial nonvolatile memory, which is coupled to the microcontroller 60 bya serial interface 67.

Circuitry involved in providing a predictable therapy of stimulation isprovided by a digital integrated circuit (IC) 70 and an analog IC 80. Inone application, the digital IC 70 contains stimulation control logic,such as the various timers that are used by the IPG's timing channels toprovide a stimulation pulse train with a particular timing. The analogIC 80 receives data from the digital IC 70 via a serial link, where suchdata is converted to analog signals by a digital-to-analog converter(DAC) 82, which in turn ultimately provides the stimulus to theelectrodes (E1 . . . EN). Additionally, an analog-to-digital (A/D)converter 74 is used to inform the microcontroller 60 of various analogvoltages being produced or monitored on the analog IC 80, such asvarious reference voltages, the stimulation compliance voltage, etc.,and within the charging 64 and telemetry 62 blocks. Although shown asintegrated with the microcontroller 60, the A/D converter 74 could alsobe a discrete component outside of the microcontroller 60.

In one embodiment, the microcontroller 60, the digital IC 70, and theanalog IC 80 comprise discrete ICs each comprising one of the components20 on the IPG's printed circuit board 16 (see FIG. 1). Other functionalblocks in the architecture 50 might comprise other components 20, whichmight not be integrated but rather formed at least in part of discretecomponents.

Having briefly described the functional blocks in architecture 50, itshould be noted that it is not important to the present disclosure tounderstand the detailed workings of those blocks. (The reader canconsult the above-incorporated '898 application should a greaterknowledge of each of the functional blocks be desired). Instead, what isimportant to understand is the manner in which the functional blocks areinterconnected. As one skilled in the art will understand, central tothe operation of architecture 50 is the microcontroller 60, whichultimately receives and issues all commands from and to the otherblocks. Furthermore, it can be noticed that the various interconnectionsbetween the blocks vary in type and complexity, with some connectionsbeing serial in nature, and others comprising single data lines orcomprising data digital busses. Moreover, some of the blocks lack directconnections with other blocks, and hence must communicate throughintermediary blocks. For example, the microcontroller 60 must, at leastin part, communicate with the analog IC 80 through the digital IC 70.

Such inter-connectivity adds to the expense of the IPG 100 and itscomplexity. Moreover, it also makes it difficult to adapt a particulararchitecture to desired changes and/or newer IPG revisions. For example,the changing of one of the functional blocks may require significantcorresponding changes in other functional blocks, making upgrades orrevisions expensive.

Additionally, space within an IPG 100 is limited, because IPGs arepreferably as small as possible to make the implant as unobtrusive aspossible for the patient. In this regard, the architecture 50 of FIG. 3is further problematic because of its requirement of separate IC usedfor the microcontroller 60, the digital IC 70, and the analog IC 80 (andpossibly other components). Having numerous components generallynegatively impacts the reliability of the circuit, and increases powerconsumption, generally a big concern for a power-limited IPG.

This disclosure presents a solution to this problem in the art ofimplantable medical devices via an improved IPG architecture.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show an implantable pulse generator (IPG), and themanner in which an electrode array is coupled to the IPG in accordancewith the prior art.

FIG. 2 shows the IPG in relation to an external charger in accordancewith the prior art.

FIG. 3 shows the architecture of the circuitry within the IPG inaccordance with the prior art.

FIG. 4 shows an improved architecture for an IPG incorporating acentralized bus operating with the various functional blocks inaccordance with a communication protocol.

FIG. 5 shows the various signal on the centralized bus of FIG. 4 andindicates the communication protocol used on the bus.

FIG. 6 shows the basic structure of the bus interface circuitry used byeach functional block communicating with the centralized bus of FIG. 4.

FIG. 7 shows how the improved architecture of FIG. 4 easily provides foradditional memory or controller resources outside of an IPG IC built inaccordance with the architecture of FIG. 4.

FIG. 8 shows various registers useful in sharing control between anexternal controller and a controller internal to an IPG IC built inaccordance with the architecture of FIG. 4.

FIG. 9 shows the circuitry useful for sharing control between theexternal and internal controller of FIG. 8.

FIG. 10 shows a flow chart discussing the operation of the circuitry ofFIG. 9.

DETAILED DESCRIPTION

An improved architecture for an implantable medical device such as animplantable pulse generator (IPG) is disclosed. In one embodiment, thevarious functional blocks for the IPG are incorporated into a singleintegrated circuit (IC). Each of the functional blocks communicate witheach other, and with other off-chip devices if necessary, via acentralized bus governed by a communication protocol. To communicatewith the bus and to adhere to the protocol, each circuit block includesbus interface circuitry adherent with that protocol. Because each blockcomplies with the protocol, any given block can easily be modified orupgraded without affecting the design of the other blocks, facilitatingdebugging and upgrading of the IPG circuitry. Moreover, because thecentralized bus can be taken off the integrated circuit, extra circuitrycan easily be added off chip to modify or add functionality to the IPGwithout the need for a major redesign of the main IPG IC.

FIG. 4 shows one example of the improved IPG architecture 150. As acomparison to FIG. 3 shows, most of the functional blocks in FIG. 4correspond to circuit blocks of FIG. 3, and thus perform similarfunctions in the new architecture 150. However, in a major difference,all of the functional blocks in the improved architecture 150 arecoupled to a centralized bus 190. In the embodiment illustrated in thisdisclosure, the centralized bus 190 is a parallel bus containing aplurality of multiplexed address and data lines operating in parallel.However, this is not strictly necessary, and instead bus 190 cancomprise a serial bus as well.

In a preferred embodiment, each of the illustrated functional blocks areintegrated within a single integrated circuit (IC) 200. Because the IPGIC 200 as illustrated contains both analog and digital signals, the IC200 would comprise a mixed mode chip. However, it is not strictlynecessary that the architecture 150 be realized on a single IC 200 asshown. Moreover, it should be understood that certain other circuitrycomponents within the IPG 100 (such as the data and charging coils 96and 18, the power source 26, and external memory 66, etc.) wouldlogically reside outside of the IC 200. That being said, it is stillpreferred that as many as possible of the functional blocks within theIPG be consolidated on the IC 200, as this increases yield, increasesreliability, decreases space of the electronic circuitry within the IPG,decreases power consumption of the circuitry within the IPG 100, etc.

Each of the various functional blocks in the improved IPG architecture150 communicate with the centralized bus 190 via bus interface circuitry215, which will be discussed in further detail later. Preferably, allother non-bus-based communications between the functional blocks arekept to a minimum, but some such communications are beneficial. Forexample, as shown, various interrupts (INT1, INT2, . . . ) communicatedirectly with an interrupt controller 173, which allows their issuanceto be immediately recognized without the potential delays involved inprotocol-based communication through the centralized bus 190. Forexample, INT2 can inform the interrupt controller 173 if the powersource 26 is charged to a dangerous level, so that operation of the IC200 might be temporarily curtailed if necessary. In another off-buscommunication, an analog bus 192 is used to send various analog signalsto a A/D block 74 where such voltages can be digitized and madeavailable to other functional blocks via the centralized bus 190 asneeded.

While it is not terribly important to the disclosed improved IPGarchitecture 150 to understand the operation of each of the functionalblocks, note from FIG. 4 that the digital IC 70 and the analog IC 80 ofthe prior art (FIG. 3) have effectively been consolidated into amixed-mode stimulation circuitry block 175, which both sets the timing,magnitude, and polarity of the stimulation pulses appearing at each ofthe electrodes, Ex.

In another important difference with the architecture 50 of the priorart (FIG. 3), notice that the centralized microcontroller 60 (FIG. 3)has been replaced by an internal controller 160. Given the parallelednature of the centralized bus 190, control within the IC 200 is lessfocused on one source, and instead control is essentially dividedbetween the controller 160 and the various functional blocks, with thecontroller 160 acting as the “master.” Specifically, each functionalblock contains set up and status registers (not shown). The controller160, upon initialization, writes to the set up registers to configureand enable each functional block. The status registers are then set byeach functional block and read by the controller 160 to query for statusand other results. Aside from such control imposed by the mastercontroller 160, many of the functional blocks outside of the controller160 can employ simple state machines to manage their operation, whichstate machines are enabled and modified via the set up registers.Because it acts as the master, the bus interface circuitry 215 of theinternal controller 160 is somewhat unique and, for example, containsdriver circuitry 216 for the control signals used by the communicationsprotocol (e.g., ALE, W/E, and R/E) which would be lacking in the businterface circuitry 215 of other functional blocks within the IC 200.

As can be seen in FIG. 4, the IC 200 contains several external terminals202 (e.g., pins, solder bumps, etc.), such as those necessary to connectthe power source 26, to connect the coils 18, 96, to connect theexternal memory 66, and to connect the stimulation electrodes. In apreferred embodiment, other external terminals 202 are dedicated to thevarious signals that comprise the centralized bus 190 to allow this busto communicate with other devices outside of the IC 200, as will beexplained in more detail later.

The various signals comprising the bus 190 can be seen in FIG. 5, whichalso discloses one possible protocol for communications on the bus. Asshown, the centralized bus 190 comprises a clock signal (CLK) forsynchronization, time-multiplexed address and data signals (A/Dx); anaddress latch enable signal (ALE); an active-low write enable signal(*W/E), and an active-low read enable signal (*R/E). The centralized bus90 may comprise sixteen address/data signals, but of course this numbercan change depending on system requirements.

As one skilled in the art will appreciate, communications in an IPGsystem such as one including the IC 200 of FIG. 4 can operate relativelyslowly compared to other computerized systems. This eases therequirements of the protocol used on the centralized bus 190, and allowsfor a relatively simple and comparatively-slow protocol to be used. Forexample, the frequency for the clock signal, CLK, can be in the range of32 kHZ to 1 MHz. Such a frequency is generally slow for a computerizedprotocol, but is suitably fast compared to operation of the IPG, whichtypically provide stimulation pulses on the order of tens ofmicroseconds to milliseconds.

As shown, the protocol uses a fairly simple address-before-data schemein which an address is followed by pertinent data for that address, etc.To help discern between address and data, the address latch enablesignal (ALE) is active only upon the issuance of an address, whichallows the address to be latched upon the rising edge of the clock.Whether the data corresponding to a particular address is to be writtenor read depends on the assertion of the write and read enable signals(*W/E; *R/E). Of course, this protocol is merely exemplary and otherprotocols and formats could be use for communication on the centralizedbus 190.

The nature of the protocol of FIG. 5 means that all functional blockscoupled to the centralized bus 190 must be designated an address, ormore likely, a range of addresses. For example, the address for a dataregister holding the value for the compliance voltage (in A/D block 74)might be ADDR[3401] while the address for a bandgap reference voltagemight be ADDR[3402]; the address for the magnitude of stimulation to beprovided by electrode E6 (in stimulation circuitry block 175) may beADDR[7655], while the duration of that pulse may be stored atADDR[7656], etc.

To assist the various functional blocks in recognizing pertinentaddresses, and to ensure each block's ability to function in accordancewith the centralized bus 190's protocol, each block contains businterface circuitry 215, which is shown in FIG. 6. One skilled in theart will well understand the operation of bus interface circuitry 215,and so it is explained at a general level. As noted earlier, one or moreaddresses may be associated with each functional block, such asADDR[1]-[5] in the simple example of FIG. 6. When such addresses arereceived at the various blocks, each block decodes those addresses todetermine a match, i.e., to determine if the address corresponds to oneof the addresses pointing to that block. If so, and depending of whetherdata is to be written to of read from the address in question, busdrivers (in the case of a read) or bus receivers (in the case of awrite) are enabled, and the data is then written to or read from theblock's data register. To adhere to this protocol, the actual functionalcircuitry in the block (not shown in FIG. 6) must interface with thedata register appropriately as one skilled in the art understands.

With the bus interface circuitry 215 allowing each functional block tocommunicate using the protocol established for the bus 190, it nowbecomes a relatively simple endeavor to make changes to the variousfunctional blocks to fix circuit errors, and/or to upgrade the IC 200for use in next-generation IPGs. This is because each of the blocks'circuitry can be changed without worries that such changes willnecessitate other changes in related blocks, or otherwise perturb theoperation of other blocks. Functional blocks can be independentlydesigned and verified in parallel, saving time and hassle during thedesign process.

Another advantage of the improved architecture 150 is the ability toeasily modify or add functionality to the IPG 100 outside of the IC 200.For example, future improvements may require the IPG to store more datathan is otherwise available in the on-chip memory 177 or the off-chipmemory 66 (see FIG. 4). In such a case, and if the centralized-busarchitecture 150 is used within the IC 200, the bus 190 may be extendedoutside of the IC 200 as shown in FIG. 7, and more memory 300(preferably, nonvolatile memory) added. This is of great benefit,because it allows the IPG circuitry to be upgraded without to need toredesign the IC 200 and/or some of its functional blocks.

In another example showing how the disclosed architecture 150 benefitssystem integration, the capacity of the system can be effectivelydoubled by the addition of another IC 200′ similarly constructed to thefirst IC 200. This would allow the IPG 100 in which the IC 200 and 200′were placed to provide 32 stimulation electrodes, i.e., 16 each fromboth of the ICs. In other words, the capacity of the IPG can beincreased by simply “daisy chaining” a plurality of stimulation ICstogether. In such an embodiment, it may be beneficial that the internalcontroller 160 in one of the ICs 200 or 200′ be inactivated so only onecontroller 160 acts as the master controller for the system.Alternatively, the IPG system can utilize both controllers 160 in bothof the ICs 200 and 200′, although this requires arbitration between thetwo controllers to prevent potential conflicts, a subject discussedbelow with reference to FIGS. 8-10.

Other devices may also be added external to the IC 200 via the bus 190.For example, one particularly interesting application enabled by the useof architecture 150 is the ability to place at least some degree ofsystemic control outside of the IC 200. For example, in FIG. 7, anexternal microcontroller 240 is used to supplant or augment the internalcontroller 160 resident within the IC 200. (The external microcontroller240 could comprise the internal controller 160 of an additional IC 200′,a point discussed above). Again, the ability to control the IPG via anexternal controller means that the programming for the IPG can bechanged without changes to the IC 200 or the various functional blocks.

However, to add additional control via an external microcontroller 240,additional communications may be required between the internalcontroller 160 and the external microcontroller 240 to ensure noconflict between the two control mechanisms. FIG. 8-10 describe how theinternal controller 160 and external microcontroller 240 can sharecontrol of the IC 200 without conflict.

In recognition of the possibility of external control, the internalcontroller 160 is provided with additional functionality as illustratedin FIGS. 8 and 9. By way of a quick preview, this additionalfunctionality is designed to recognize whether a particular commandissued on the bus 190 is to be handled by the internal controller 160 orthe external microcontroller 240. Which device 160 or 240 ultimatelyprocesses the command at issue is set by a controller select bit (CSB).If CSB=0, the internal controller 160 executes the command in question;if CSB=1, the external controller 240 executes the command. As can beseen in FIGS. 7 and 9, CSB can comprise a discrete communication signalgenerally outside of the scope of the centralized bus 190, which due toits discrete nature can be a preferable implementation as a faster andsafer method of arbitration between the two controllers 160 and 240.

In other implementations, the controller select bit can comprise datasent via the bus 190 using the bus 190's protocol. In such animplementation, the CSB data could be viewed as a control “token” whichis passed between the internal controller 160 and the externalmicrocontroller 240 via the bus 190. Such a purely bus-based method forarbitration between the controllers is easily implemented. However,because it is easier to illustrate the passage of control between thetwo controllers 160 and 240 using a discrete non-bus based signalapproach, that approach is illustrated below and in the figures.

As shown, the internal controller 160 is designed with two registers, acommand register 220 and a command owner register 230, shown in detailin FIG. 8. The command register 220 is a standard feature of manycontrollers, and simply comprises a binary representation of the variouscommands the IPG can execute. In the example shown, because the commandregister 220 is eight bits long, the IPG 100 is capable of processing256 (2̂8) different commands. The command owner register 230 is comprisedof as many bits as there are relevant commands (in this example, 256),with each bit in the register denoting whether a particular command isto be handled by the internal controller 160 or the externalmicrocontroller 240. As shown, if particular bit in the command ownerregister 230 is a ‘0 ’, the corresponding command is to be executed bythe internal controller 160; and if a ‘1,’ the external microcontroller240 will execute the command. In a simple example, if the 256-bitcommand owner register 230 reads ‘1010000 . . . 0001,” commands 256,254, and 1 (CMD256, CMD254, and CMD1) would be executed by the externalmicrocontroller 240, with all other commands executed by the internalcontroller 160.

The use of command register 220 and command owner register 230 to issuea controller select bit (CSB) 245 is illustrated in FIG. 9. Once acommand has been received by the command register 220, it is decoded(e.g., demultiplexed) to understand its command number (CMD256 to CMD1).Then, the command number is used to retrieve the appropriate commandowner bit from the command owner register 230. This bit is set as thecontroller select bit (CSB) 245 to indicate which controller (160, 240)is to handle the command as mentioned earlier.

This process is explained in detail with respect to FIG. 10. Upon bootup, the command owner register 230 is loaded with default values frommemory (internal memory 177, serial external memory 66, etc.). Normally,the default values of the various command owner bits in the commandowner register 230 would be all ‘0’s, denoting that at least initiallyall commands are to be executed by the internal controller 160.Thereafter, at some point during operation, the command register 220 isloaded with a command at its address (ADDR[CMD]). The command is decoded(demultiplexed) as explained above, and the corresponding command ownerbit is issued as the controller select bit (CSB) 245. The CSB 245 isalso stored in the controller enable register 250 at its address(ADDR[CER]), which may comprise a single bit, as shown in FIG. 9. TheCSB 245 is also sent to the external controller 240.

With the CSB 245 issued, it is now known which of the controllers 160 or240 is to execute the command in question, and thus various actions aretaken accordingly. If CSB=‘0 ’, denoting the internal controller 160,little needs to be accomplished but for that controller 160 to executethe command. As a default, to ensure that the external microcontroller240 will not conflict with execution of the command by the internalcontroller 160, arbitration logic 246 programmed into the externalcontroller 240 disables the external controller's bus drivers 242 uponsensing that CSB=0. In contrast, the internal controller bus drivers 212are enabled by the stored controller enable register bit 250 (an activelow signal). After the internal controller 160 has executed its command,the system waits for the next command, and the method repeats, etc.

However, if CSB=‘1’, denoting the external microcontroller 240, extrasteps are taken to allow control to be temporarily shifted to theexternal microcontroller 240. Specifically, the arbitration logic 246 inthe external controller recognizes upon sensing that CSB=‘1’ that it isin control, and enables its bus drivers 242. By contrast, the internalcontroller bus drivers 212 are disabled. Additionally, upon recognizingthat CSB=‘1’, the arbitration logic 246 retrieves the command (i.e., itscommand) as stored in the command register 220 by requesting a read viathe bus 190 from that register's address (ADDR[CMD]). Once received, theexternal controller 240 executes the command.

With the command executed by the external microcontroller 240, theremaining steps illustrated in FIG. 10 are directed to returning controlback to the internal controller 160 prior to the receipt of a nextcommand. After execution of the command, the arbitration logic 246 nowwrites a ‘0’ in the controller enable register 250, which can beaccessed via the bus 190 at its address ADDR[CER]. This in turn onceagain enables the bus drivers 212 for the internal controller 160.Concurrent with overwriting the controller enable register 250, thearbitration logic 246 disables the bus drivers 242 for the externalcontroller 240. This restores the system to its initial state in whichthe internal controller 160 assumes control by default, at which pointthe system awaits its next command, and the method repeats, etc.

The flow of FIG. 10 is just one way to allow the internal and externalcontrollers 160 and 240 to operate together without conflict inaccordance with the improved centralized bus architecture 150. However,one skilled in the art will recognize that other flows and circuitry arepossible for achieving this same goal, and therefore what is depictedshould be understood as merely an example.

Although particular embodiments of the present invention have been shownand described, it should be understood that the above discussion is notintended to limit the present invention to these embodiments. It will beobvious to those skilled in the art that various changes andmodifications may be made without departing from the spirit and scope ofthe present invention. Thus, the present invention is intended to coveralternatives, modifications, and equivalents that may fall within thespirit and scope of the present invention as defined by the claims.

1. An implantable stimulator device comprising a plurality of firstelectrodes and a plurality of second electrodes configured to providestimulation to a patient's tissue, comprising: a first integratedcircuit comprising a first stimulation circuitry block for controllingstimulation of the plurality of first electrodes; a second integratedcircuit comprising a second stimulation circuitry block for controllingstimulation of the plurality of first electrodes; and a bus incommunication with both the first and second integrated circuits,wherein communications on the bus occurs in accordance with a busprotocol.
 2. The device of claim 1, wherein the first and secondstimulation circuitry blocks respectively comprise first and seconddigital-to-analog converter circuitry for respectively providingstimulation to the plurality of first and second electrodes.
 3. Thedevice of claim 1, further comprising an electrode array coupled to thefirst and second electrodes.
 4. The device of claim 3, wherein theelectrode array comprises a plurality of electrode leads.
 5. The deviceof claim 1, further comprising a controller in communication with thebus, wherein the controller controls the first and second integratedcircuits via the bus.
 6. The device of claim 5, wherein the controllercomprises an integrated circuit separate from the first and secondintegrated circuits.
 7. The device of claim 5, wherein the controllerresides on one of the first or second integrated circuits.
 8. The deviceof claim 1, wherein the first and second integrated circuits aresimilarly constructed.
 9. The device of claim 1, wherein the protocolcomprises an address-before-data protocol.
 10. The device of claim 9,wherein the bus comprises a plurality of signals for carrying inparallel both data and addresses, wherein the data and addresses aretime-multiplexed on the plurality of signals.
 11. The device of claim10, wherein the bus comprises a write enable signal line and a readenable signal line.
 12. The device of claim 11, wherein the buscomprises an address latch enable signal line for latching a read orwrite address.
 13. The device of claim 1, wherein each of the first andsecond integrated circuits further comprises a plurality of functionalblocks each coupled to the bus.
 14. The device of claim 1, wherein thefirst and second stimulation circuitry blocks and the plurality offunctional blocks on the first and second integrated circuits eachcouple to the bus using bus interface circuitry.
 15. The device of claim1, wherein the first integrated circuit comprises a master forcontrolling the second integrated circuit as a slave.
 16. An implantablestimulator device comprising a plurality of first electrodes and aplurality of second electrodes configured to provide stimulation to apatient's tissue, comprising: a first integrated circuit comprising afirst stimulation circuitry block for controlling stimulation of theplurality of first electrodes; a second integrated circuit comprising asecond stimulation circuitry block for controlling stimulation of theplurality of first electrodes, wherein the first and second integratedcircuits are similarly constructed; and a controller for controlling thefirst and second integrated circuits.
 17. The device of claim 16,wherein the first and second stimulation circuitry blocks respectivelycomprise first and second digital-to-analog converter circuitry forrespectively providing stimulation to the plurality of first and secondelectrodes.
 18. The device of claim 16, further comprising an electrodearray coupled to the first and second electrodes.
 19. The device ofclaim 18, wherein the electrode array comprises a plurality of electrodeleads.
 20. The device of claim 16, wherein the controller comprises anintegrated circuit separate from the first and second integratedcircuits.
 21. The device of claim 16, wherein the controller resides onone of the first or second integrated circuits.
 22. The device of claim16, wherein the first and second integrated circuits and the controllerare each coupled to a communication bus, wherein communication on thebus occurs in accordance with a bus protocol.
 23. The device of claim22, wherein the protocol comprises an address-before-data protocol. 24.The device of claim 16, wherein each of the first and second integratedcircuits further comprises a plurality of functional blocks each coupledto the bus.
 25. The device of claim 24, wherein the first and secondstimulation circuitry blocks and the plurality of functional blocks onthe first and second integrated circuits each couple to a communicationbus using bus interface circuitry.